1. Field of the Invention
This invention relates generally to Schottky transistor-transistor logic (TTL) circuitry and more particularly, it relates to a non-inverting high speed low level gate to Schottky transistor-transistor logic translator circuit which requires less power consumption and exhibits a higher noise immunity from ground and supply voltage glitches.
2. Description of the Prior Art
Conventional Schottky transistor-transistor logic circuitry of the prior art are shown in FIGS. 1(a) and 1(b) which have been labeled "Prior Art". As can be seen, these prior art circuits require the use of either a pull-down resistor R3 or a pull-down resistor-transistor network formed of resistors R3, R7 and transistor Q5 to turn off the lower output transistor Q4, thereby causing a high state at the output circuit terminal Y11. These techniques require relatively high currents and thus have a high power consumption. Further, these prior art circuits have less noise immunity against large ground and supply voltage glitches.
It would thus be desirable to provide a non-inverting high speed low level gate to Schottky transistor-transistor logic translator circuit which possesses low power consumption and high noise immunity against ground and supply voltage glitches. The translator circuit of the present invention utilizes low level NAND gates adapted to receive a lower level input signal to switch the translator so as to maintain the output in an acceptable voltage and current range.